Basics of Complementary Metal Oxide Semiconductor (CMOS)

Complementary Metal Oxide Semiconductor (CMOS)

Complementary Metal-Oxide Semiconductors, or CMOS, are a manufacturing technology used to create electronic devices like microprocessors, memory chips, and sensors.

CMOS technology is widely used in portable and battery-operated electronics because it uses both N-type and P-type transistors to build very power-efficient circuits. Additionally, it enables the integration of numerous transistors onto a single chip, allowing for the development of complex electronic systems.

CMOS technology is not only highly dependable and capable of operating at high speeds, but it is also energy efficient. Due to its adaptability, low power consumption, and affordability, it has emerged as the industry standard technology for semiconductors.

These are several CMOS Gates:

1. NOT Gate

The CMOS inverter (NOT Gate) is the fundamental component of CMOS digital circuits. It inverts the input signal. A 0 (low voltage) becomes a 1 (high voltage) and vice versa. It is made up of two transistors: an NMOS transistor and a PMOS transistor are connected in series between the ground and the power supply voltage (VDD) respectively. Both transistors' gates are connected to the input, and the output is derived from the connection between them. The truth table and schematic diagram are given below.  

Working Principle:

• When the input is 0 (Low voltage):

• The NMOS transistor is OFF, blocking the path to ground (logic 0).
• The PMOS transistor being on creates a directed path for current flow from the power supply to the output, pulling it high (logic 1).
• When the input is 1 (High voltage): 
• The NMOS transistor turns ON, providing a low resistance path to the ground.
• The PMOS transistor turns OFF, isolating the output from the power supply. 
• This allows the output to be pulled down to ground (logic 0) by the conducting NMOS.

 

2. NAND Gate

The NAND gate outputs a 1 (high voltage) only when both inputs (A and B) are 1 (high voltage). Any other combination of inputs results in a 0 (low voltage) output. It consists of two NMOS transistors connected in series and two PMOS transistors connected in parallel. The truth table and schematic diagram are given below.

Working Principle: 

• When either input (A or B) is 0 (low voltage):
• The corresponding NMOS transistor connected in series will be off, blocking the current flow from the power supply to the output.
• The PMOS transistors being in parallel, even if one is on due to the other input being 1, doesn't affect the overall high resistance path. This keeps the output low (logic 0).

• When both inputs A and B are 1 (high voltage):
• Both NMOS transistors turn on, creating a direct path for current to flow from the power supply to the output, pulling it high (logic 1).
• The PMOS transistors being off in this scenario don't play a role in the current flow.

3. NOR Gate

The NOR gate outputs a 1 (high voltage) only when both inputs (A and B) are 0 (low voltage). Any other combination of inputs (0, 1 or 1, 1) results in a 0 (low voltage) output. Two PMOS transistors are connected in series, and two NMOS transistors are connected in parallel. The truth table and schematic diagram are given below.

Working Principle:

• When at least one input (A or B) is 1 (high voltage):
• The corresponding NMOS transistor will turn on, creating a low resistance path to ground (logic 0).
• This effectively pulls the output low regardless of the state of the PMOS transistors.
• When both inputs A and B are 0 (low voltage):
• Both NMOS transistors are off (high resistance).
• The PMOS transistors being in series act like a single switch. Since both are on (conduct), they provide a path for current to flow from the power supply to the output, pulling it high (logic 1).

4. AND Gate

The AND gate outputs a 1 (high voltage) only when both inputs A and B are 1 (high voltage). AND gate is the invert of the NAND gate. The truth table and schematic of the AND gate is given below.

Working Principle:

• When either input (A or B) is 0 (low voltage):
• The NMOS transistor connected to that input will be off (doesn't conduct).
• The path to ground (logic 0) is open.
• Since the PMOS transistors are in parallel, even if one is on (conducts) due to the other input being 1, it provides a low resistance path to the power supply (logic 1), keeping the output low.
• When both inputs A and B are 1 (high voltage):
• Both NMOS transistors turn on, creating a direct path for current to flow from the power supply to the output, pulling it high (logic 1).
• The PMOS transistors being off doesn't affect the current flow through the NMOS path.

5. OR Gate

The OR gate outputs a 1 (high voltage) if at least one input (A or B) is 1 (high voltage). OR gate is the invert of the NOR gate. The truth table and schematic of the OR gate are given below.

Working principle:

• When either input (A or B) is 1 (high voltage):
• The NMOS transistor connected to that input will be on (conducts), creating a low resistance path to ground (logic 0).
• The PMOS transistors being in series means even one being off (due to the other input being 0) breaks the connection to the power supply (logic 1), pulling the output low.
• When both inputs A and B are 0 (low voltage):
• Both NMOS transistors are off, offering high resistance.
• The PMOS transistors being in series act like a single switch. Since both are on (conduct) due to the low inputs, they provide a path for current to flow from the power supply to the output, pulling it high (logic 1).